1. Field of the Invention
The present invention relates to a structure and a manufacturing method of an infrared detecting element using ferroelectric thin film material to detect the intensity of infrared radiation from an object.
2. Description of the Background Art
[Background Art of Infrared Detecting Element]
Objects and human bodies at room temperature radiate infrared rays (heat rays) of approximately 10 xcexcm in wavelength which can be measured to detect the presence of them and obtain temperature information without contact. This infrared detection is applied to various uses like automatic door, intruder alarm, cooking monitor of microwave oven, chemical measurement, and the like.
The key device of prime importance for such measurement is an infrared sensor. There are generally two types of infrared sensors, i.e., quantum infrared sensor and thermal infrared sensor.
The quantum infrared sensor is highly sensitive and excellent in sensing ability while it requires cooling resulting in increase in size of the entire device and thus has a problem in practical use. On the other hand, the thermal infrared sensor is somewhat inferior to the quantum infrared sensor in terms of sensitivity while it is appropriate for practical use because of its advantage that operation at room temperature is possible.
Ferroelectric materials have temperature dependencies of both of polarization and dielectric constant as shown in FIG. 26, and these characteristics are applicable to thermal infrared sensors. The former effect is related to conventional pyroelectric (PE) bolometers and the latter effect is related to dielectric bolometers (DB).
Accordingly, various thermal infrared sensors have been proposed including those utilizing pyroelectric effect, resistance bolometer, dielectric bolometer, thermopile, Golay cell, and the like. For example, an infrared image sensor using the pyroelectric effect is disclosed in Proc. 8th IEEE Int. Symp. Appl. Ferroelectronics (1992), pp. 1-10 (xe2x80x9cPYROELECTRIC IMAGING xe2x80x9d by Bemard M. Kulwicki et al.).
In particular, the dielectric bolometer which applies electric field to detect the change of dielectric constant with respect to temperature has a higher sensitivity than those of other sensors and it requires no chopper. Because of these excellent features, the dielectric bolometers are considered prospective in terms of practical use.
Further, an advanced infrared sensing is expected that is applied to infrared image sensors (thermography) capable of providing temperature distribution of objects and scenery without contact.
In order to accomplish infrared imaging, infrared image pickup devices operating at room temperature have been produced as prototypes by bump-coupling an array of pyroelectric ceramic and a silicon FET (field effect transistor) or forming a thin-film and low-resistive bolometer on a microbridge structure which is coupled with a silicon FET array.
Regarding these devices, a higher performance is expected such as an enhanced resolution by increase in sensitivity and number of pixels and the like. However, conventional pyroelectric infrared sensors and infrared sensors in the form of resistance bolometers are limited in sensitivity or have an insufficient number of pixels.
FIG. 27 shows a cross sectional structure of a conventional pixel cell 20 in such an infrared detecting element coupled with a silicon FET array.
Referring to FIG. 27, pixel cell 20 includes a silicon oxide film 304 deposited on an Si substrate 300, a MOS transistor Tr1 formed in an opening of silicon oxide film 304, an infrared detecting capacitor CF formed being adjacent to MOS transistor Tr1 and constituted of a lower electrode 308 (stacked Pt/Ti films), a ferroelectric film 310 (BST film) and an upper electrode 312 (Al film), and a trench 330 opened to extend from the rear side of Si substrate 300 to a predetermined depth directly below infrared detecting capacitor CF.
MOS transistor Tr1 includes source/drain regions 320 and 324 formed in a main surface of the Si substrate in the opening of silicon oxide film 304 that are impurity regions of opposite polarity to that of the substrate, a channel layer 322 formed in the main surface of the Si substrate between source/drain regions 320 and 324, a gate oxide film 302 deposited on the main surface of the Si substrate directly above the channel layer, and a polysilicon gate electrode 314 formed on gate oxide film 302.
Lower electrode 308 is deposited on a silicon nitride film 306 which is deposited on silicon oxide film 304 to serve as an interlayer insulating film. Lower electrode 308 contacts source/drain region 320.
On gate electrode 314, an interconnecting line 316 is provided that is formed of the same interconnection layer as lower electrode 308, an interconnecting line 318 formed of the same interconnection layer as lower electrode 308 contacts source/drain region 324.
Trench 330 is provided in order to reduce thermal loss as much as possible to Si substrate 300 having a high thermal conductivity since pixel cell 20 is a thermal infrared sensor and a rise in temperature of the cell directly affects the intensity of an output signal.
Accordingly, it is desirable in terms of process to make the thickness of Si substrate as thin as possible that remains between trench 330 and silicon oxide film 304. On the other hand, since it is not preferable that the thickness of remaining Si substrate differs between pixel cells 20, an etching stopper layer is formed on the front side of the Si substrate when trench 330 is formed by etching from the rear side. For example, the etching stopper layer can be generated by implanting ions (e.g. at least 3xc3x971016 cmxe2x88x923 in concentration) like boron (B) from the front side of the substrate to reduce the etching rate of Si.
A method of manufacturing pixel cell 20 shown in FIG. 27 is explained below in conjunction with respective cross sections showing the first to twelfth steps of the method.
FIGS. 28 to 39 are cross sectional views respectively illustrating the first to twelfth steps.
Referring to FIG. 28, on the surface of Si substrate 300 which has been RCA-cleaned, silicon oxide film 304 is formed through thermal oxidation in the first step.
The thermal oxidation is performed under the conditions, for example, that oxidation at 1000xc2x0 C. and 51/min of oxygen flow rate for 5 minutes is performed and thereafter oxidation at 1000xc2x0 C., 51/min of oxygen flow rate and 4.51/min of hydrogen flow rate for 180 minutes is performed. The thermal oxidation under these conditions forms an about 650-nm-thick oxide film for example.
Further, an alignment mark 301 is formed on the rear side of the substrate by anisotropic dry etching or the like.
Referring to FIG. 29, in the second step, an opening is formed in a predetermined region 303 of silicon oxide film 304 by etching. MOS transistor Tr1 is formed in this region 303 as described later.
Referring to FIG. 30, a resist pattern 305 is used as a mask for ion implantation of ion species into channel portion 322 of MOS transistor Tr1, the ion species corresponding to the conductivity type of the channel portion 322. Then, annealing is performed for activation.
Referring to FIG. 31, gate oxide film 302 is deposited on the Si substrate through thermal oxidation and thereafter a polysilicon 307 is deposited by CVD (Chemical Vapor Deposition) or the like that forms the gate electrode.
Referring to FIG. 32, polysilicon 307 is patterned and etched by anisotropic etching like RIE (Reactive Ion etching) to form gate electrode 314.
Referring to FIG. 33, the gate pattern is used as a mask to etch away gate oxide film 302 on opening 303 and silicon oxide film 304, and then gate electrode 314 and silicon oxide film 304 are used as a mask to diffuse impurities to generate source/drain regions 320 and 324.
Referring to FIG. 34, silicon nitride film 306 is deposited by CVD or the like.
Silicon nitride film 306 is formed under the conditions for example of 780xc2x0 C., 0.015 l/min of SiC12H2, 0.060 l/min of NH3, 26.7 Pa and 60 minutes so that a silicon nitride film of approximately 300 nm is deposited.
Referring to FIG. 35, the rear side of the wafer is patterned by means of resist to etch away the silicon nitride film and the silicon oxide film. Then, trench 330 is formed directly below infrared detecting capacitor CF in Si substrate 300 by anisotropic wet etching from the rear side of the substrate under the conditions of etchant of TMAH 22%, 100xc2x0 C. and 180 minutes. The size of opening of the trench is for example several tens of xcexcmxc3x97several tens of xcexcm. The depth of etching is approximately 250 xcexcm.
The thickness of the Si substrate directly below infrared detecting capacitor CF is in the range of 0 to 50 xcexcm for example, preferably as thin as possible to the extent that the mechanical strength is secured as discussed above.
In other words, preferably the Si substrate is etched away directly under infrared detecting capacitor CF so that no Si substrate is present.
Referring to FIG. 36, a contact hole (connection hole) is formed by RIE or the like that opens on source/drain regions 320 and 324 of MOS transistor Tr1 and on gate electrode 314.
Referring to FIG. 37, stacked Pt/Ti films are formed that constitute lower electrode 308 and interconnecting lines 316 and 318 by means of lift-off technique or the like including patterning by resist, film deposition by sputtering or vacuum evaporation, and acetone and ultrasonic cleaning. When the film deposition is performed by RF sputtering, the Ti film is formed by the sputtering under the conditions of 0.00532 l/min of Ar, 0.6 Pa and RF power of 500 W for 3 minutes and the Pt film is formed by the sputtering under the conditions of 0.00532 l/min of Ar, 0.6 Pa, RF power of 200 W for 8 minutes. Following these conditions, the Ti film of 60 nm and the Pt film of 160 nm in thickness are generated.
Referring to FIG. 38, a BST film or the like is deposited for ferroelectric film 310 by laser ablation method or the like. The laser ablation enables the ferroelectric film to be deposited at a low substrate temperature so that the substrate where an FET array is formed is less damaged.
Referring to FIG. 39, Al film 312 is formed by sputtering, vacuum evaporation or the like into a predetermined pattern to constitute the upper electrode.
Pixel cell 20 having the cross sectional structure as shown in FIG. 27 is thus produced through these steps.
Pixel cell 20 shown in FIG. 27 is a dielectric bolometer utilizing field-induced pyroelectric effect. The bolometer operates as an infrared sensor by using change of the dielectric constant with temperature.
As described above, the thickness of the Si substrate directly below infrared detecting capacitor CF is desirably 0 xcexcm.
In order to achieve this, after the step shown in FIG. 39, the Si substrate is dry-etched from the rear side of the wafer using the silicon nitride and oxide films as a mask. The etching may be performed under the conditions of 0.0075 l/min of SF6 gas, 13.3 Pa and RF power of 50 W for approximately 30 minutes.
A problem as explained below arises when trench 330 is formed by etching of the Si substrate from the rear side to the front surface thereof.
FIG. 40 is a plan view illustrating a state resultant from complete etching of the Si substrate immediately below infrared detecting capacitor CF so that the thickness of the Si substrate becomes 0 xcexcm. FIG. 41 is a cross section along XLIxe2x80x94XLI in FIG. 40
As shown, a portion is held on the trench after the etching leaving no Si substrate directly under infrared detecting capacitor CF. That portion is called xe2x80x9cmembranexe2x80x9d and such a structure is referred to as xe2x80x9cmembrane structure.xe2x80x9d
A problem of this membrane structure is distortion of the membrane as shown in FIG. 41 resultant from influence of film stress and the like caused by the multilayer structure of infrared detecting capacitor CF consisting of the underlying insulating film, lower electrode, ferroelectric thin film, upper electrode and the like.
The film stress may be alleviated by forming films with respective stresses in reverse directions into the multilayer structure. However, in order to stack films so that respective stresses are cancelled with respect to each other, precise management and control of the film thickness and stress value are necessary for each layer of the stacked films, which complicate the process in vain.
Moreover, a considerable time is required for etching the Si substrate from the rear side to form trench 330 so that etchant could deteriorate characteristics of the ferroelectric thin film.
One object of the present invention is to provide an infrared two-dimensional image sensor which can be integrated easily and enhanced in detecting sensitivity.
In summary, according to an aspect, the present invention is an infrared detecting element formed on a main surface of a substrate that includes an infrared detecting capacitor having a capacitance value changing according to temperature change caused by absorption of infrared radiation. The infrared detecting capacitor includes a trench formed in the substrate, first and second interconnecting lines extending from both sides of the trench, and a capacitor portion. The capacitor portion is shaped to have three pairs of opposing sides in plan view, one pair of opposing vertex parts of the capacitor portion supported by the first and second interconnecting lines to be held on the trench. The capacitor portion includes an upper electrode coupled to the first interconnecting line, a lower electrode opposing the upper electrode and coupled to the second interconnecting line, and a ferroelectric thin film provided between the upper and lower electrodes. The infrared detecting element detects the change of the capacitance value of the infrared detecting capacitor to sense infrared radiation.
According to another aspect of the present invention, an infrared two-dimensional image sensor includes a plurality of pixel cells arranged in a form of matrix. The pixel cells each include an infrared detecting capacitor having a capacitance value changing according to temperature change caused by absorption of infrared radiation. The infrared detecting capacitor includes a trench formed in the substrate, first and second interconnecting lines extending from both sides of the trench, and a capacitor portion shaped to have three pairs of opposing sides in plan view, one pair of opposing vertex parts of the capacitor portion supported by the first and second interconnecting lines to be held on the trench. The capacitor portion includes an upper electrode coupled to the first interconnecting line, a lower electrode opposing the upper electrode and coupled to the second interconnecting line, and a ferroelectric thin film provided between the upper and lower electrodes. The change of the capacitance value of the infrared detecting capacitor is detected to sense infrared radiation.
According to still another aspect of the present invention, a method of manufacturing an infrared detecting element includes the steps of: forming on a main surface of a substrate a first interconnecting line and a lower electrode metal layer; forming a ferroelectric layer on the lower electrode metal layer; depositing a first insulating film on the ferroelectric layer; forming on the first insulating film an upper electrode metal layer and a second interconnecting line; anisotropically wet etching the substrate beneath the lower electrode metal layer from the main surface of the substrate to form a trench such that the lower electrode metal layer, the ferroelectric layer and the upper electrode metal layer are supported by the first and second interconnecting lines.
According to a further aspect of the present invention, a method of manufacturing an infrared detecting element includes the steps of: forming an MgO film on a main surface of a substrate; forming on the MgO film a first interconnecting line and a lower electrode metal layer; forming a ferroelectric layer on the lower electrode metal layer; forming on the ferroelectric layer an upper electrode metal layer and a second interconnecting line; and anisotropically wet etching the substrate beneath the lower electrode metal layer from the main surface of the substrate to form a trench such that the lower electrode metal layer, the ferroelectric layer and the upper electrode metal layer are supported by the first and second interconnecting lines.
According to a still further aspect of the present invention, a method of manufacturing an infrared detecting element includes the steps of: depositing a first insulating film on a main surface of a substrate and patterning the first insulating film into a shape including a predetermined shape in plan view; anisotropically wet etching the substrate beneath the predetermined shape of the first insulating film from the main surface of the substrate to form a trench such that the predetermined shape constitutes a membrane supported with respect to the main surface of the substrate; forming a first interconnecting line and a lower electrode metal layer for the membrane; forming a ferroelectric layer on the lower electrode metal layer; depositing a second insulating film on the ferroelectric layer; and forming on the second insulating film an upper electrode metal layer and a second interconnecting line.
According to a still further aspect of the present invention, a method of manufacturing an infrared detecting element includes the steps of: depositing a first insulating film on a main surface of a substrate; forming an MgO film on the first insulating film and patterning the first insulating film and the MgO film into a shape including a predetermined shape in plan view; anisotropically wet etching the substrate beneath the predetermined shape of the first insulating film from the main surface of the substrate to form a trench such that the predetermined shape constitutes a membrane supported with respect to the main surface of the substrate; forming a first interconnecting line and a lower electrode metal layer on the membrane; forming a ferroelectric layer on the lower electrode metal layer; and forming on the ferroelectric layer an upper electrode metal layer and a second interconnecting line.
Pixel cells having the infrared detecting elements according to the present invention can be used to achieve an infrared detecting circuit of a simple structure having a high sensitivity at room temperature. A two-dimensional sensor array having such pixel cells arranged in two dimension can be used to achieve an infrared two dimensional image sensor operating at room temperature with a high sensitivity and highly dense pixels.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.